Gecko's CPU Library

AMD Opteron (Sledgehammer, Venus, Troy, Athens) processors

Introduction: April 2003 (Sledgehammer), August 2005 (Venus)


The Opteron was AMD's x86 server processor line, and was the first processor to implement the AMD64 instruction set architecture (known generically as x86-64). It was released on April 22, 2003 with the SledgeHammer core (K8) and was intended to compete in the server market, particularly in the same segment as the Intel Xeon processor.

The Sledgehammer, Venus, Troy and Athens cores

Opteron combined two important capabilities in a single processor die: native execution of legacy x86 32-bit applications without speed penalties and native execution of x86-64 64-bit applications.

The first capability was notable because at the time of Opteron's introduction, the only other 64-bit processor architecture marketed with 32-bit x86 compatibility (Intel's Itanium) ran x86 legacy-applications only with significant speed degradation. The second capability, by itself, was less noteworthy, as all major RISC makers (Sun SPARC, DEC Alpha, HP PA-RISC, IBM POWER, SGI MIPS, etc.) had 64-bit implementations for many years. In combining these two capabilities, however, the Opteron had earned recognition for its ability to run the vast installed base of x86 applications economically, while simultaneously offering an upgrade-path to 64-bit computing.

The Opteron processor possessed an integrated DDR/DDR2 SDRAM (Socket AM2/F) memory controller. This both reduced the latency penalty for accessing the main RAM and eliminates the need for a separate northbridge chip.

In multi-processor systems (more than one Opteron on a single motherboard), the CPUs communicated using the Direct Connect Architecture over high-speed HyperTransport links. Each CPU was able to access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing was not the same as standard symmetric multiprocessing as instead of having one bank of memory for all CPUs, each CPU had its own memory. Thus the Opteron was a Non-Uniform Memory Access (NUMA) architecture. The Opteron CPU directly supported up to an 8-way configuration, which could be found in mid-level servers. Enterprise-level servers used additional (and expensive) routing chips to support more than 8 CPUs per box.

In a variety of computing benchmarks, the Opteron architecture had demonstrated better multi-processor scaling than the Intel Xeon. This was primarily because adding an additional Opteron processor increases bandwidth, while that was not always the case for Xeon systems, and the fact that the Opterons used a switched fabric, rather than a shared bus. In particular, the Opteron's integrated memory controller allowed the CPU to access local RAM very quickly. In contrast, multiprocessor Xeon system CPUs shared only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increased in a Xeon system, contention for the shared bus caused computing efficiency to drop.

First generation single-core Opterons followed the three-digit "Opteron xyy" model numbers and going forward the newer generations (all dual cores) were four-digit in the form "Opteron xnyy":
- The first digit (the x) specified the maximum number of CPUs on the target machine: "1" designed for uniprocessor systems, "2" designed for dual-processor systems, "8" designed for systems with 4 or 8 processors.
- The n digit was the release number (omitted in first release). The major differences between release one and release two included different socket type (socket 940 vs. socket F), single-core vs. dual core, quad-core upgradeability, support for DDR1 vs. DDR2 memory and for AMD Virtualization.
- The last two digits in the model number (the yy) gived an indication of the relative performance comparison among models of the processors.
- Models with an HE label refered to a low-power deviative with 55W & 68W lower TDP value, while products with a SE label refered to a high performance processor with higher TDP values.

Source: Wikipedia, the free encyclopedia.