Gecko's CPU Library

DEC T-11 processors

Introduction: 1981

The T-11 (code name Tiny) was DEC's third microprocessor design, and the first single chip design. Rich Olsen and then Mary Ellen Lewandowski were the lead project engineers; Dan Dobberpuhl's consulting company did the circuit design and layout.

The T-11 had a substantially different focus than the F-11. It aimed to capitalize on the strength of the PDP-11 in embedded markets by providing a one chip, inexpensive, low-power PDP-11 with a standard interface. Its target markets were OEM's and embedded devices rather than systems.

The T-11 had the same feature set as the LSI-11 (no floating point, no memory management) but the integer performance of the F-11. It was implemented in a scaled version of the F-11 process (5u NMOS) and operated at 250Mhz (400ns microcycle). The T-11 dissipated less than 1.2W and cost less than $10 in high volume.

The T11's (DC310) key features are:
- Transistors: 17,000 sites
- Basic PDP-11 instruction set (except MARK)
- Industry standard external interface
- Vectored interrupt subsystem (4 priority levels, 15 internally generated vectors)
- Dynamic memory support (RAS/CAS addressing, strobe generation, automatic refresh)
- Programmable 8-bit or 16-bit external data bus
- Programmable start and restart addresses
- Internal clock oscillator
- Single +5V supply

The T-11 was always a bit of a stepchild in the Semiconductor Group. Because it wasn't targeting systems, it was prioritized lower than projects that generated systems revenue. Nonetheless, after release it was widely used inside DEC for smart controllers (like the RQDX3) and auxiliary processors (like the KXV21), and outside DEC in applications as diverse as arcade games (Atari's Paperboy) and laboratory instruments.

Source: Unknown.