• Home
• Documentations
• Packages
• Sockets
• Links
• Contacts

Hewlett Packard PA-7000 (Cheetah) processors

Introduction: 1991

The PA-7000 was the first PA-RISC 1.1 CPU implementation and saw its first uses in the first PA-RISC 700 series workstations and later on in some of the Nova servers. It was still a multi-chip implementation.

The PA-7000 was used in 705/35, 710/50, 720/50, 730/66, 750/66, F10, F20, F30, G30, G40, H20, H30, H40, I30 and I40.

- PA-RISC version 1.1a 32-bit

- Needs external FPU (commonly used was a coprocessor developed by HP and Texas Instruments)

- Five-stage pipeline

- 96/96 I/D TLB

- 4/4 I/D BTLB

- 32-bit bus to I cache

- 64-bit bus to D cache

- Off-chip caches up to 256KB/256KB I/D

- Up to 66MHz frequency with 5.0V core voltage

- 14.2×14.2 mm2 die, 577,000 FETs, 1.0 micron, 2-layer CMOS (FPU fabbed in 0.8 micron)