• Home
• Documentations
• Packages
• Sockets
• Links
• Contacts

AMD K5 (SSA/5, 5k86) processors

Introduction: March 1996

The K5 was developed by AMD to compete with Intel's Pentium microprocessor range. Introduced in 1996 over a year late, AMD's problems were compounded by being unable to manufacture the chip at the clock speeds originally projected. In its favor, the K5 did at least offer good x86 compatibility. All models had 4.3 million transistors on-chip. No K5 supported MMX instructions.

Internally ambitious, it was closer to a Pentium Pro than a Pentium, based upon an internal highly parallel 29k RISC processor architecture with an x86 decoding front-end.

- Five integer units, which could process instructions out of order, one floating point unit, compared to two units of the Pentium.

- The branch target buffer was four times the size of the Pentium's, although not reportedly more accurate.

- Register renaming improved parallel performance of the pipelines.

- Speculative execution of instructions reduced pipeline stall.

- The instruction cache was 16KB, double the Pentium.

- The primary cache was 4-way set associative instead of the Pentium's 2-way.

The K5 project represented an early chance for AMD to take technical leadership from Intel. Although the chip addressed the right design concepts, the actual engineering implementation was weak. The low clock rates were due in part to AMD's deficiencies as a manufacturing company in the period. However, having a branch prediction unit four times the size of the Pentium, yet reportedly not delivering superior performance, is an example of how the actual implementation fell short of the project goals. Additionally, while the K5's floating point performance was better than that of the Cyrix 6x86, it was weaker than that of the Pentium. Because it was late to market and did not meet performance expectations, the K5 never gained the acceptance among large computer manufacturers that the Am486 and AMD K6 enjoyed. Overall, the chip failed to deliver, both in terms of raw performance, and financially for AMD.

There were two sets of K5 processors, internally called the SSA/5 and the 5k86, both released with the K5 label. The SSA/5 line ran from 75 to 100MHz (5k86 P75 to P100, later K5 PR75 to PR100); the 5k86 line ran from 90 to 133MHz. However, AMD used what it called a PR rating, or performance rating, to label the chips according to their equivalence to a Pentium of that clock speed. Thus, a 116MHz chip from the second line was marketed as the K5 PR166.