Cyrix 6x86 (M1, M2) processors
Introduction: 1996
The Cyrix 6x86 is a sixth-generation, 32-bit x86-compatible microprocessor designed by Cyrix and manufactured by IBM and SGS-Thomson. It was originally released in 1996.
The 6x86 combines aspects of both RISC and CISC. It has a superscalar, superpipelined core, and performs register renaming, speculative execution, out-of-order execution, and data dependency removal. However, it continued to use native x86 execution, like Centaur's Winchip, but unlike competitors Intel and AMD who moved to RISC translation with Pentium Pro and K5.
With regards to internal caches, it has a 16KB primary cache and is socket-compatible with the Intel Pentium P54C. It was also unique in that it was the only x86 design to incorporate a 256-byte Level 0 scratchpad cache. It has six performance levels: PR 90+, PR 120+, PR 133+, PR 150+, PR 166+ and PR 200+. These performance levels do not map to the clock speed of the chip itself (for example, a PR 133+ ran at 110MHz, a PR 166+ ran at 133MHz, etc).
Note that the 6x86 and 6x86L weren't completely compatible with the Intel Pentium instruction set. For this reason the chip identified itself as a 80486 and disabled the CPUID instruction by default. CPUID support could be enabled by first enabling extended CCR registers then setting bit 7 in CCR4. The lack of full Pentium compatibility caused problems with some applications because programmers had begun to use Pentium-specific instructions. Some companies released patches for their products to make them function on the 6x86.
The first generation of 6x86 had heat problems. This was primarily caused by their relatively higher heat output than other CPUs of the day and, as such, computer builders sometimes did not equip them with adequate cooling. The CPUs topped out at around 25W heat output (like the AMD K6), whereas the Pentium produced around 15W of waste heat at its peak.
6x86 is not multi-processor capable.
The 6x86's integer performance was fantastic. As said earlier, Cyrix used a PR rating (Performance Rating) to relate their performance to the Intel Pentium Classic (pre-P55C), because a 6x86 at a lower clock rate outperformed the higher-clocked Pentium. For example, a 133MHz 6x86 will outperform a Pentium Classic at 166MHz, and as a result Cyrix could market the 133MHz chip as being a Pentium 166's equal. A PR rating was also necessary because the 6x86 could not clock as high as Pentium and maintain equivalent manufacturing yields, so it was critical to establish the slower clock speeds as equal in the minds of the consumer. The PR rating was not an entirely truthful representation of the 6x86's performance, however.
While it can be simply said that its integer performance is excellent, the same can not be said with regard to its floating point performance. The FPU is considerably less robust than that of the Pentium (let alone the P6 FPU.) During the 6x86's development, the majority of applications (office software) performed almost entirely integer operations. The designers foresaw that future applications would most likely maintain this instruction focus. So, to optimize the chip's performance for what they believed to be the most likely application of the CPU, the integer execution resources received most of the transistor budget.
The poor FPU performance of the 6x86 can be mostly attributed to major FPU instructions taking at least 4 clock cycles and that it was not pipelined. It was not much faster than a 486 FPU at the same clock speed. The popularity of the Pentium caused many software developers to hand-optimize code in assembly language, to take advantage of the Pentium's pipelined and lower latency FPU. For example, the highly anticipated first person shooter Quake used highly-optimized assembly code designed almost entirely around the Pentium's FPU. As a result, the Pentium significantly outperformed other CPUs in the game. Fortunately for the 6x86 (and AMD K6), many games continued to be integer-based throughout the chip's lifetime.
The 6x86 successor, MII, was late to market, and couldn't scale well in clock speed. Cyrix had made a mistake with 6x86, similar to what AMD had done with their K5; design a chip far more focused on integer per-clock performance superiority than clock scalability. As such, 6x86 and MII were forced to compete at the low-end of the market because AMD K6 and Intel Pentium II were always at least one step ahead on clock speed. This, combined with the limited floating point unit, and an integer section that was at best on-par with the newer P6 and K6 chips, Cyrix could no longer compete in performance.
Source: Wikipedia, the free encyclopedia.