VIA C3 (Nehemiah) processors
Introduction: January 2003
Overview
The VIA Cyrix III/C3 was a family of x86 central processing units for Socket 370 personal computers, designed by Centaur Technology and sold by VIA Technologies. The different CPU cores were built following the design methodology of Centaur Technology.
The VIA Cyrix III was later renamed VIA C3, as it was not built upon Cyrix technology at all.
The Nehemiah core
The "Nehemiah" (C5XL) was a major core revision. At the time, VIA's marketing efforts did not fully reflect the changes that had taken place. The company addressed numerous design shortcomings of the older cores, including incomplete MMX compatibility and the half-speed FPU. The number of pipeline stages was increased from 12 to 16, to allow for continued increases in clock speed. Additionally, it implemented support for the cmov instruction, making it a 686-class processor. The Linux kernel refers to this core as the C3-2. It also removes 3DNow! instructions in favour of implementing SSE. However, it was still based upon the aging Socket 370, running the single data rate front side bus at just 133 MHz.
Because the embedded system marketplace prefers low-power, low-cost CPU designs, VIA began targeting this segment more aggressively because the C3 fit those traits rather well. Centaur Technology concentrated on adding features attractive to the embedded marketplace. An example built into the first "Nehemiah" (C5XL) core were the twin hardware random number generators.
The "C5P" revision of "Nehemiah" brought with it a few more advancements, including a high-performance AES encryption engine along with a notably small ball grid array chip package the size of a US 1 cent coin.
Source: Wikipedia, the free encyclopedia.