PA-RISC architecture
Introduction: 1986
PA-RISC is a microprocessor architecture developed by Hewlett-Packard's Systems & VLSI Technology Operation. As the name implies, it is an implementation using a RISC (Reduced Instruction Set Computing) design, where the PA stands for Precision Architecture. The design is also referred to as HP/PA for Hewlett Packard Precision Architecture. PA is considered by some to stand for Palo Alto, the location of HP's headquarters.
In the late 1980s HP was building four series of computers, all based on CISC CPUs. One line was the IBM PC compatible Intel i286 based Vectra Series started 1986. All others were non-Intel systems. One of them was the HP Series 300 of Motorola 68000-based workstations (in 1990 they had one additional 68000-based Series, the new HP Apollo Series 400, a workstation line they took over when they purchased Apollo Computer in 1989), another Series 200 line of technical workstations based on a custom silicon on sapphire (SOS) chip design, the SOS based 16-bit HP 3000 classic series and finally the HP 9000 Series 500 minicomputers, based on their own (16 and 32-bit) FOCUS CPU. HP planned to use the PA-RISC to move all of their non-PC compatible machines to a single RISC CPU family.
The early PA-RISC chips were 32-bit designs. They were first used in a new series of HP 3000 machines in the late 1980s — the 930 and 950, commonly known at the time as Spectrum systems, the name given to them in the development labs. These machines ran MPE/iX. The HP 9000 machines were soon upgraded with the PA-RISC processor as well, running the HP-UX version of UNIX.
Other operating systems ported to the PA-RISC processor include Linux, OpenBSD, NetBSD, NEXTSTEP, and an unreleased Windows NT.
An interesting aspect of the PA-RISC line is that most of its generations have no Level 2 cache. Instead large Level 1 caches are used, formerly as separate chips connected by a bus, and now integrated on-chip. Only the PA-7100LC and PA-7300LC had L2 caches. Another innovation of the PA-RISC was the addition of vectorized instructions (SIMD) in the form of MAX which were first introduced on the PA-7100LC.
The design was upgraded in 1996 to the PA-RISC 2.0 architecture, which is fully 64-bit. The first product of this series was the PA-8000, which featured ten functional units and an aggressive pipelining system. Another change was the splitting of the instruction cache, with separate caches for instructions that take long or short time to complete. The PA-8200 was released in 1997 and was much like the PA-8000 with better branch prediction, lower TLB miss rates, and larger, faster caches.
The core design introduced with the PA-8000 has not changed significantly to date; each later generation has concentrated only on increasing clock speed and integrating incremental improvements like larger caches and, finally, 2 cores on one chip. Along with the MIPS architecture, the PA-RISC is nearing the end of its lifecycle as a commercial UNIX-machine CPU.
Source: Wikipedia, the free encyclopedia.