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POWER architectureIntroduction: 1990POWER architecture began its life at IBM in the late 1980s when they wanted a high performance RISC architecture for their mid range workstations and servers. The result was the POWER architecture with its first implementation in 1990 in the RISC System/6000, later RS/6000, computers. This was the 11-chips RIOS processor, later called POWER1. The RISC Single Chip (RSC) processor was developed from RIOS. POWER is a backronym for Performance Optimization With Enhanced RISC. The instruction set architecture is divided into several categories and every component is defined as a part of a category. And each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor use categories Server, Base, Floating Point, 64-bit, etc. All processors implement the Base category.
Instructions have a 4-byte (32-bit) uniform length with the exception of the VLE (Variable-Length Encoding) subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precision IEEE-754 compliant floating point operations are supported with additional multiply add instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction. Support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. Support for both big and little-endian addressing with separate categories for moded and per-page endianess. Support for both 32-bit and 64-bit addressing. Different modes of operation: User, supervisor and hypervisor.
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