Intel iAPX 432 processors
Introduction: January 1981
The Intel iAPX 432 was Intel's first 32-bit microprocessor design, introduced in 1981 as a set of three integrated circuits. The iAPX 432 was intended to be Intel's major design for the 1980s, implementing many advanced multitasking and memory management features in hardware, which led them to refer to the design as the Micromainframe.
The processor's data structure support allowed modern operating systems to be implemented on it using far less program code than ordinary CPUs; the 432 would instead do much of the work internally in hardware. However, the design was extremely complex compared to the mainstream microprocessors of the era, so much so that Intel's engineers weren't able to translate the design into an efficient implementation using the semiconductor technology of its day. The resulting CPU was very slow and expensive, and so Intel's plans to replace the x86 architecture with the iAPX 432 ended miserably.
The abbreviation iAPX prefixing the model name reportedly stands for intel Advanced Processor architecture, the X coming from the Greek letter Chi.
The iAPX 432 was originally planned to have a clock speed of 10 MHz, but the available models were actually 5, 7, and 8 MHz. It operated at a top speed of 2 million instructions per second.
The 432 project started in 1975 as the 8800, so named as a follow-on to the existing 8008 and 8080 CPUs. The design was intended to be purely 32-bit from the outset, and be the backbone of Intel's processor offerings in the 1980s. As such it was to be considerably more powerful and complex than their existing "simple" offerings. However the design was well beyond the capabilities of the existing process technology of the era, and had to be split into several individual chips.
The core of the design was the two-chip General Data Processor (GDP) which was the main processor. The GDP was split in two, one chip (the 43201) handling the fetching and decoding of the instructions, the other (the 43202) executing them. Most systems would also include the 43203 Interface Processor (IP) which operated as a channel controller for I/O. The two-chip GDP had a combined count of approximately 97,000 transistors while the single chip IP had approximately 49,000, making them some of the largest IC designs of the era. By way of comparison, the Motorola 68000 (introduced in 1979) had approximately 68,000 transistors.
In 1983 Intel released two additional integrated circuits for the iAPX 432 Interconnect Architecture, the 43204 Bus Interface Unit (BIU) and 43205 Memory Control Unit (MCU). These chips allowed for nearly glueless multiprocessor systems with up to 63 nodes.
Several design features of the iAPX 432 conspired to make it much slower than it could have been. The two-chip implementation of the GDP limited it to the speed of the motherboard's electrical wiring, although this is a minor issue. The lack of reasonable caches and registers was considerably more serious. The instruction set also hindered performance by using bit-aligned variable-length instructions, as opposed to word-aligned fixed-length instructions used in the majority of designs, making instruction decoding complex and slow. In addition the BIU was designed to support fault-tolerant systems, and in doing so added considerable overhead to the bus, with up to 40% of the bus time in wait states.
Post-project research suggested that the biggest problem was in the compiler, which used high-cost "general" instructions in every case, instead of high-performance simpler ones where it would have made sense. For instance the iAPX 432 included a very expensive inter-module procedure call instruction, which the compiler used for all calls, despite the existence of much faster branch and link instructions. Another very slow call was enter_environment, which set up the memory protection. The compiler ran this for every single variable in the system, even though the vast majority were running inside an existing environment and didn't have to be checked. To make matters worse it always passed data to and from procedures by value rather than by reference, requiring huge memory copies in many cases.
An outcome of the failure of the 432 was that microprocessor designers concluded that object support in the chip leads to a complex design that will invariably run slowly, and the 432 was often cited as a counter-example by proponents of RISC designs. However it is held by some that the OO support was not the primary problem with the 432 and that the implementation shortcomings mentioned above would have made any chip design slow. Since the iAPX 432 there has been only one other attempt at a similar design, the Rekursiv processor, although the INMOS Transputer's process support was similar - and very fast.
Intel had spent considerable time, money and mindshare on the 432, had a skilled team devoted to it, and were loath to abandon it entirely after its failure in the marketplace. A new architect, Glenford Myers, was brought in to produce an entirely new architecture and implementation for the core processor, which would be built in a joint Intel/Siemens project (later BiiN), resulting in the i960-series processors. The i960 RISC subset became popular for a time in the embedded processor market, but the high-end 960MC and the tagged-memory 960MX were marketed only for military applications and saw even less use than the 432.
Source: Wikipedia, the free encyclopedia.