Gecko's CPU Library

DEC J-11 processors

Introduction: 1983

The J-11 (code name Jaws, which the design team never used) was DEC's fourth and last PDP-11 microprocessor design, and the first to be done in CMOS. The project was co-developed with Harris Semiconductor. Bob Supnik was the project leader through 1981, then Dan Casaletto. Paul Rubinfeld was lead engineer on the Data chip, Gil Wolrich on the Control chip and the FPA. Keith Henry wrote the microcode. Circuit design and layout were done by Harris Semiconductor.

The J-11 was intended to put a "capstone" on the PDP-11 family by providing the full functionality and performance of the PDP-11/70 in a microprocessor. Accordingly, the J-11 incorporated most of the architectural ornamentation from the 11/70 - dual register sets, data space, supervisor mode - as well as more modern inventions such as SMP support. Microcode-based floating point was standard, with accelerated floating point available as an option. CIS microcode was also intended to be an option.

The J-11 was a chip set consisting of three designs, one of which could be replicated: the Control chip (up to three supported), the Data chip, and the optional FPA chip. The Control and Data chips were implemented in Harris double-poly 4µ P-well CMOS. The FPA was implemented in DEC's double-metal 3µ NMOS process (ZMOS).

The Data chip (DC334) implements the instruction execution and memory management data paths of the J-11 chip set. It shares with the Control chip responsibility for the external interface and for instruction prefetching. The data chip operates under the control of microwords fetched from the Control chip(s). Its key features are:
- Transistors: 40,000
- Execution unit
- PDP-11 architectural general registers (16b): dual register set, three stack pointers
- Processor status word (PSW)
- Microcode temporary registers (32b)
- Full function arithmetic/logic unit (32b)
- Single bit shifter
- Byte swapper
- Conditional branch logic
- Memory management unit
- External interface sequencer
- Instruction prefetch logic
- Power: 0.5W

The Control chip (DC335) implements the microword access and sequencing functions of the J-11 chip set. Its key features are:
- Transistors: 80,000 sites
- ROM/PLA control store (512 x 25b PLA terms, 768 ROM terms)
- Chip set microsequencer
- External interface sequencer
- Instruction prefetch logic
- Power: 0.5W

The J-11 FPA (DC321) is a high performance, single chip, floating point accelerator for the J-11 chip set. Its key features are:
- Transistors: 34,000
- High performance: accelerates floating point execution by 5X
- f_ and d_floating point format support
- Full PDP-11 floating point instruction set, including MODf
- Arithmetic error checking and reporting
- Single +5V supply
- Power: 2.5W

The J-11 was introduced late in 1983 at 3.75Mhz; subsequent tweaks pushed the performance to 4.5Mhz. The FPA was introduced in 1984. The FPA was used as the basis for the MicroVAX Floating Point Unit and the V-11 F chip.

Source: Unknown.