Gecko's CPU Library

Hewlett Packard TS-1 processors

Introduction: 1986

The TS-1 was the very first production processor ot the PA-RISC family and integrated version 1.0 of PA-RISC on six boards (each 8.4×11.3") of TTL: I-unit (Instruction Unit, controls the instruction flows, executes branches and handles interrupts and traps etc.), Register File Board (contains the 32 32-bit general registers GR0-GR31 and 25 control registers in SRAMs), E-unit (Execution Unit, performs arithmetic and address calculation with the integer ALU, does also load and store operations), TLB (Translation Lookaside Buffer with 4096 entries for 2KB pages), Cache controller (contains the split instruction and data caches - 64KB for each I and D) and FPC (Floating-Point Coprocessor, handles FP operations parallel to the CPU/ALU). Each board contained about 150 ICs. TS-1 processors were only used in the 840 server systems.

- PA-RISC version 1.0 32-bit
- External FPU (the ADD/MUL/DIV chip was taken over from the HP 9000/550 FOCUS system)
- Three-stage pipeline
- 4096-entry TLB off-chip, direct-mapped
- Off-chip L1 cache of 128KB (I/D) direct-mapped/one-way associative
- Physical address space of 27-bit (128MB main memory could be addressed)
- 8MHz clock speed
- Six (some sources say five) printed circuit boards, implemented in FAST TTL and (25ns and 35ns) SRAMs/PALs