Gecko's CPU Library

Hewlett Packard NS-1 processors

Introduction: 1987

The first implementation of PA-RISC (1.0) in a NMOS fabrication process followed shortly on the original TTL-based TS-1 and was called accordingly NS-1. It implemented the central processing unit on a single chip and needed several other ICs to complete the whole processor (including external FPU and cache chips).

The NS-1 processor is contained on one circuit board (two on 825) and integrates the complete CPU as a single NMOS-III chip, accompanied by eight other (NMOS-III) VLSI chips: SIU (System Interface Unit), two CCUs (Cache Controller Units CCU0 and CCU1), TCU (TLB Controller Unit), MIU (Math Interface Unit, which speaks to the FP chips) and three third-party floating point (FP) chips (ADD, MUL and DIV). Cache and TLB memory was implemented in separate chips, their sizes varying on the different computer models - from 16KB up to 128KB cache and TLBs with 2048 up to 4192 entries.

- PA-RISC version 1.0 32-bit
- External third-party FPU
- Three-stage pipeline
- 2048-4096-entry TLB off-chip
- Off-chip L1 cache of 16KB (HP 9000/825) to 128KB (others), unified
- Physical address space of 29-bit (512MB main memory could be addressed)
- 25-30MHz clock speed
- One circuit board (two boards on HP 9000/825), 144,000 FETs, implemented in NMOS-III packaged in a 272-pin ceramic PGA package
- CPU itself is a single chip, accompanied by eight other VLSI chips (cache/TLB, FPU and I/O and bus attachments)