Hewlett Packard NS-1 processors
Introduction: 1987
The first implementation of PA-RISC (1.0) in a NMOS fabrication process followed shortly on the original TTL-based TS-1 and was called accordingly NS-1. It implemented the central processing unit on a single chip and needed several other ICs to complete the whole processor (including external FPU and cache chips).
The NS-1 processor is contained on one circuit board (two on 825) and integrates the complete CPU as a single NMOS-III chip, accompanied by eight other (NMOS-III) VLSI chips: SIU (System Interface Unit), two CCUs (Cache Controller Units CCU0 and CCU1), TCU (TLB Controller Unit), MIU (Math Interface Unit, which speaks to the FP chips) and three third-party floating point (FP) chips (ADD, MUL and DIV). Cache and TLB memory was implemented in separate chips, their sizes varying on the different computer models - from 16KB up to 128KB cache and TLBs with 2048 up to 4192 entries.
Source: www.openpa.net