Intel 80960 processors
Introduction: April 1988
Intel's 80960 (or i960) was a RISC-based microprocessor design that became quite popular during the early 1990's as an embedded microcontroller, for some time likely the best-selling CPU in that field, pushing the AMD 29000 from that spot. In spite of its success, Intel formally dropped i960 marketing in the late 1990's as a side effect of a lawsuit with DEC, in which Intel received the rights to produce the StrongARM CPU.
The i960 design was started as a response to the failure of Intel's iAPX 432 design of the early 1980's. The iAPX 432 was intended to directly support high-level languages that supported tagged, protected, garbage-collected memory in hardware. Because of its instruction-set complexity, its multi-chip implementation, and other design flaws, the iAPX 432 was very slow in comparison to other processors of its time.
The first i960 processors "taped-out" in October 1985 and were sent to manufacturing that month, with the first working chips arriving in late 1985 and early 1986. Myers tried to convince Intel management to market the i960 (then still known as the "P7") as a general-purpose processor, both in place of the Intel 80286 and 80386 (which "taped-out" the same month as the first i960), as well as the emerging RISC market for Unix systems, including a pitch to Steve Jobs's for use in the NeXT system.
Myers was unsuccessful at convincing Intel management to support the i960 as a general-purpose or Unix processor, but the chip found a ready market in early high-performance 32-bit embedded systems. The protected-memory architecture was considered proprietary to BiiN and wasn't mentioned in the product literature, leading many to wonder why the i960MC was so large and had so many pins labeled "no connect".
A version of the RISC core without memory management or an FPU became the i960KA, and the RISC core with the FPU became the i960KB. The versions were, however, all identical internally - only the labelling was different.
The "full" i960MX was never released for the non-military market, but the i960MC was used in high-end embedded applications and i960KA became successful as a low-cost 32-bit processor for the laser-printer market, as well as for early graphics terminals and other embedded applications. Its success paid for future generations, which removed the complex memory sub-system.
The i960CA, first announced in July 1989, was the first pure RISC implementation of the i960 architecture. It featured a newly-designed superscalar RISC core and added an unusual addressable on-chip cache, but lacked an FPU and MMU, as it was intended for high-performance embedded applications. The i960CA is widely considered to have been the first single-chip superscalar RISC implementation. The C-Series only included one ALU, but could dispatch and execute an arithmetic instruction, a memory reference, and a branch instruction at the same time, and sustain two instructions per cycle under certain circumstances. The first versions released ran at 33Mhz, and Intel promoted the chip as capable of 66 MIPS. The i960CA microarchitecture was designed in 1987-1988 and formally announced on September 12, 1989.
Later, the i960CF included a floating-point unit, but continued to omit an MMU.
In 1990 the i960 team was redirected to be the "second team" working in parallel on future i386 implementations - specifically the P6 processor, which later became the Pentium Pro. The i960 project was sent to another, smaller development team, essentially ensuring its ultimate demise.
Source: Wikipedia, the free encyclopedia.