Gecko's CPU Library

Hewlett Packard NS-2 processors

Introduction: 1989

The last NMOS-based PA-RISC processor was the NS-2, a tweaked follow-on to the NS-1 with increased pipeline stages (from three to five), new TLB and cache controllers and significantly larger caches (1MB) and TLBs (16K).

The NS-2 design was simplified over its NS-1 predecessor. The processor is contained on one processor circuit board and integrates the CPU as a single NMOS-III chip, with seven other VLSI (NMOS-III) chips on its side: SIU (System Interface Unit), two CCUs (Cache Controller Units, split into instruction and data - ICCU and DCCU), TCU (TLB Controller Unit), FPC (Floating Point Controller, speaks to the FP chips) and two third-party floating point (FP) chips (ADD, MULTI). The bus structure connecting these chips was updated (and simplified), with the CPU having private connections to the cache and TLB controllers (for which the NS-1 CPU had to use the shared cache bus).

- PA-RISC version 1.0 32-bit
- External third-party FPU
- Five-stage pipeline
- 16384-entry TLB off-chip
- Off-chip L1 cache up to 1024KB, split into I/D
- Physical address space of 29-bit (512MB main memory could be addressed)
- 27.5MHz clock speed
- One circuit board, implemented in NMOS-III
- CPU itself is a single chip, needs seven VLSI support chips for cache/TLB, FPU and memory/bus interfaces