Gecko's CPU Library

IBM POWER1 processors

Introduction: February 1990

February 1990 IBM announces its new RISC-based computer line, the RISC System/6000 (later named RS/6000, nowadays eServer pSeries), running AIX Version 3. The architecture of the systems is given the name POWER (now commonly referred to as POWER1), standing for "Performance Optimization With Enhanced RISC". They where based on a multiple chip implementation of the 32-bit POWER architecture. The models introduced included an 8KB instruction cache (I-cache) and either a 32KB or 64KB data cache (D-cache). They had a single floating-point unit capable of issuing one compound floating-point multiply-add (FMA) operation each cycle, with a latency of only two cycles and optimized 3-D graphics capabilities.

The model 7013-540 (30MHz) processed 30 million instructions per second. Its electronic logic circuitry had up to 800,000 transistors per silicon chip. The maximum memory size was 256MB and its internal disk storage capacity was 2.5GB.