IBM PowerPC 601 processors
Introduction: September 1993
The PowerPC 601 was the first generation of microprocessors to support a subset of the PowerPC instruction set. It was introduced at the same time as IBM POWER2 line of processors. Basically it is a simplified and thus cheaper version of the RISC Single Chip (RSC) processor, with support for some PowerPC instructions not in the POWER instruction set added. Worth noting is that it didn't include all the PowerPC instructions, so it acted more like a bridge between the POWER and the future PowerPC processors. It also included the 60x bus technology from Motorola's 88110 RISC-processors. It was designed in just 12 months and was pushed hard to establish PowerPC on the market early.
The chip was designed to suit several applications and had support for external L2 cache and symmetric multiprocessing. It had a four stage pipeline, 4 functional units, including a floating point unit, an integer unit, a branch unit and a sequencer unit (a little used heritage from the RSC). The processor also included a memory management unit.
It was launched in 1993, manufactured by both IBM and Motorola, using a 0.6 µm aluminum based CMOS process, at speeds ranging from 50 to 80MHz. The die was 121 mm² large, had 2.8 million transistors and included 32KB unified L1 cache which was very much at the time. Thanks partly to the large cache it was considered a high performance processor in its segment, readily beating Intel's competitor Pentium. PowerPC 601 was used in the first Power Mac computers from Apple, and in some RS/6000 machines from IBM.
An updated version, PowerPC 601v, 74 mm² small using a 0.5 µm fabrication process, followed in 1994 with speeds 100-120MHz.
Source: Wikipedia, the free encyclopedia.