Gecko's CPU Library

Hewlett Packard PA-7100LC (Hummingbird) processors

Introduction: 1994

The PA-7100LC was primarily designed as a single-chip solution for application in low cost systems while still delivering the performance of 1991 high-end workstations and servers. Contrary to earlier PA-RISC version 1.1 implementations which needed several support chips for the MPU the PA-7100LC integrates the CPU, FPU, MIOC (memory and I/O controller) and a first-level cache on a single VLSI chip. Both CPU and FPU support the PA-RISC 1.1 Edition 3 ISA.

PA-7100LC was used in 712/{60,80,100}, 715/{64,80,100}, 725/100, 743i/{64,100}, 748i/{64,100}, D200, D210, D300, D310, E25, E35, E45, E55, Hitachi 3050RX 225, 235 and SAIC Galaxy 1100.

- PA-RISC version 1.1c 32-bit
- Three functional units: 2 integer ALUs, 1 Floating Point unit
- 2-way superscalar
- Five-stage pipeline
- DRAM-memory & cache controller (MIOC) integrated on die
- 1KB on-chip I L1 instruction cache, direct mapped, 64-bit per access, prefetch from off-chip I cache
- 8KB-2MB off-chip unified I/D L1 cache, direct mapped, hashed address, virtual index, 480-600MB/s bandwidth
- The 1KB on-chip I cache is not really considered a true cache, thus the off-chip cache in fact is the system’s real L1 cache
- 32-Byte cache line size
- Support for bi-endian load-store operations
- MAX-1 multimedia extensions (subword arithmetic) for multimedia applications, e.g. MPEG decoding
- Floating Point load-store to I/O space
- 64-entry unified I/D TLB, fully associative, 4K page size
- 8-entry BTLB, page sizes from 512K-64M
- 64-bit wide load/store operations
- I and D cache bypassing
- Stall on use D cache miss policy
- Don’t fill on miss cache hint
- Hardware TLB miss handler support
- Hardware static branch prediction
- GSC bus interface
- 64-bit ECC interface to the main memory
- Instruction line prefetch from main memory
- Up to 100MHz clock
- Not MP capable
- 14.2×14.2 mm2 die, 900,000 FETs, 0.75 micron, 3-layer aluminium process packaged in a 432-pin PGA