Gecko's CPU Library

MIPS R8000 processors

Introduction: 1994

The R8000 was the first superscalar MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16KB instruction and 16KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the Power Indigo2 workstation. Its limited integer performance and high cost dampened appeal for most users, although its FPU performance fit scientific users quite well, and the R8000 was in the marketplace for only a year and remains fairly rare.

Source: Wikipedia, the free encyclopedia.