Gecko's CPU Library

Hewlett Packard PA-7200 (Thunderbird') processors

Introduction: 1995

The PA-7200 is leveraged from the original PA-7100 design, big parts of the core were just shrunk for the new 0.55 micron CMOS14A process. The FPU was taken over completely unchanged, retaining the same latencies for addition and multiplication even at a higher clock rate. It also acquired the cache design, e.g. had (for the time) big off-chip caches clocked at full CPU speed (140MHz). This chip was aimed at high-performance general-purpose applications but also on specialized applications that used large working sets which could take advantage of the high-bandwidth bus interface.

PA-7200 was used in C100, C110, D250, D260, D350, D360, J200, J210, K100, K200, K210, K220, K400, K410, K420, Convex SPP1200/{CD,XA} and Convex SPP1600/{CD,XA}.

- PA-RISC version 1.1d 32-bit
- Three functional units: 2 integer ALUs, 1 Floating Point
- 2-way superscalar
- FPU, MMU, cache controller integrated on die
- Five-stage pipeline
- 2KB on-chip assist L1 cache, fully associative, holds 64 32-Byte cache lines
- Off-chip L1 caches up to 1MB I and 2MB D realized in asynchronous SRAMs with one cycle latency
- The 2KB on-chip assist cache is not really considered a true cache, thus the off-chip cache is the system’s de-facto L1 cache
- Caches are 64-bit per access, direct mapped, parity protected and cycled at CPU speed
- Caches are virtually indexed and physically tagged to minimize latency
- 120-entry fully associative TLB
- 16-entry BTLB
- Hardware TLB miss support
- Six predecode bits
- Support for uncached memory pages
- Bi-endian support
- System speed interface speed programmable to 1.0, 0.75 and .67 processor speed
- Runway system/memory bus, 64-bit wide, 120MHz, 960MB/s max. bandwidth
- Glueless interface to the system bus for up to four-way SMP (four CPUs on same Runway processor bus)
- Can have up to six bus-transactions in progress at once
- Up to 140MHz frequency with 4.4V core and 3.3V I/O voltage
- 14.0×15.0 mm2 die, 1,300,000 FETs, 0.55 micron, 3-layer metal CMOS (CMOS14A process) packaged in a 540-pin ceramic PGA package
- Power dissipation of 29W at 140MHz