IBM PowerPC 602 processors
The 602 is a low-cost, low-power implementation of the PowerPC microprocessor family of reduced instruction set computing (RISC) microprocessors. The 602 implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floatingpoint data types of 32 and 64 bits. Floating-point operations involving 64-bit data types are not implemented in the 602. Double-precision floating point operations are trapped for emulation in software.
The 602 integrates four execution units - an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), and a load/store unit (LSU). The ability to execute four instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for 602-based systems. Most integer instructions execute in one clock cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.
The 602 provides independent on-chip, 4KB, two-way set-associative, physically addressed caches for instructions and data as well as on-chip instruction and data memory management units (MMUs).
The 602 has a single bus interface used for transferring both 32-bit addresses and 64-bit or 32-bit data. This bus is time-multiplexed. First the address is driven on the bus, and then the data. During each address phase, the 602 samples the T32 input pin to determine if the data phase will use a 32-bit bus or a 64-bit bus.
The 602 uses an advanced, 3.3V CMOS process technology and maintains full interface compatibility with TTL devices.