Gecko's CPU Library

Hewlett Packard PA-7300LC (Velociraptor) processors

Introduction: 1996

The PA-7300LC is the direct descendant of the PA-7100LC and likewise designed for low-cost systems. It is still a PA-RISC 1.1 32-bit processor, in contrast to the new PA-RISC 2.0 64-bit PA-8000 introduced in the same timeframe. While the PA-7300LC is rather close to the original PA-7100LC design it has several significantenhancements: large on-chip L1 caches (in contrast to the small assist caches of the 7100LC and 7200), integrated L2 controller onto the MIOC and improved bus interface (faster GSC).

The then current process technologies made it possible to include a large L1 cache on the CPU die, breaking a long-standing HP tradition of (large) off-chip L1 caches. The PA-7300LC was the last PA-RISC version 1.1 CPU, all later workstations and servers used 64-bit PA-RISC 2.0 processors.

PA-7300LC was used in 744/{132L,165L}, 745/132L, 745/165L, 748/132L, 748/165L, A180, A180C, B132L, B132L+, B160L, B180L+, C132L, C160L, D220, D230, D320, D330, RDI PrecisionBook 132, 160, 180 and Hitachi 3050RX 255, 355E, 365E.

- PA-RISC version 1.1e 32-bit
- Three functional units: 2 integer ALUs, 1 Floating Point unit
- 2-way superscalar
- MAX-1 multimedia extensions (subword arithmetic) for multimedia applications (not explicitly mentioned on the PA7300LC, but its documentation states support for MAX-1 instructions)
- 64KB/64KB I/D on-chip L1 caches, each two-way set associative, virtually indexed
- Cache line size of 32 Byte
- Caches have a 64-bit datapath to the execution units, 256-bit datapath to main memory
- Optional unified I/D L2 off-chip cache, up to 8192KB
- No hashing for both I and D caches
- L2 cache is write-through, direct mapped, physically indexed and physically tagged
- Instruction prefetch buffer moved from memory controller to L1 instruction cache, thus allowing prefetch hits without penalty
- On-chip MIOC memory controller
- 96-entry unified I/D TLB
- 8-entry BTLB
- 4-entry ILAB
- GSC system bus interface (implements GSC+ features), maximum clock frequency of 40MHz - actual system implement from 33MHz (132MB/s), 36MHz (140MB/s) and up to 40MHz (160MB/s)
- Either 64-bit or 128-bit datapath from execution units to the memory
- Up to 180MHz frequency with 3.3V core voltage
- 15.3×17.0 mm2 die, 9,200,000 FETs, 0.5 micron, 4-layer metal CMOS (CMOS14C process) packaged in a 464-pin ceramic PGA package