Gecko's CPU Library

Hewlett Packard PA-8500 (Vulcan) processors

Introduction: September 1998

The PA-8500 is a direct evolution of the PA-8000 and PA-8200 processors; the processing core was taken over incorporating only minor changes. However, for the first time in a PA-RISC CPU, a large L1 cache was integrated directly onto the CPU die, breaking with a long-standing HP tradition of keeping the L1 caches off-chip (although the two years older PA-7300LC processor already included an albeit smaller L1 cache on-chip). Some of the other improvements include bigger TLB and BHT. The PA-8500 is a full 64-bit chip and as such supports a flat 64-bit virtual address space, although only 40 physical address bits are used by the chip, corresponding to one Terabyte of directly addressable memory. Backward compatibility to older 32-bit PA-RISC CPUs is provided.

The big challenge in developing the PA-8500 was its huge on-chip cache. It had to fit onto the allocated die area and be able to keep up with the IRB. A similar cache design to that of its predecessors was used, although the RAM cells for the cache now sat directly on the die. The data cache is composed of 0.5MB banks, implemented with four 0.125MB arrays providing error correction. The data is organized in such way that either a full cache line can be addressed at once or four ways of associativity together. The instruction cache is implemented as one bank of 0.5MB four-way set associative pipelined cache, providing 128 bits of instruction plus pre-decode bits per cycle.

As his predecessors the PA-8500 is able to execute instructions speculatively; the processor guesses the path of the ongoing instructions and executes them in this path. If the guess is found to be incorrect, the speculatively executed instructions are discarded. Speculative execution is aided by a branch prediction mechanism based on the branch history table (BHT).

PA-8500 was used in A400-44 (rp2400), A500-44 (rp2450), B1000, B2000, C360, C3000, J5000, J7000, L1000-36, L1000-44 (rp5400), L2000-36, L2000-44 (rp5450), N4000-36, N4000-44 (rp7400), V2500 and Stratus Continuum 419, 429, 616S, 616, 619, 629, 1219, 1229.

- PA-RISC version 2.0 64-bit
- Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
- 4-way superscalar
- Two address adders
- 160-entry fully-associative dual-ported TLB
- 32-entry BTAC (Branch Target Address Cache)
- 2048-entry BHT (Branch History Table)
- Dynamic and static branch prediction modes
- On-chip L1 caches 0.5MB I and 1MB D, each 4-way set associatve
- 32 or 64 Byte cache line size
- Supports up to 1 TB of physically addressable memory (40-bit physical addresses)
- 56-entry instruction queue/reorder buffer (IRB)
- MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g. MPEG decoding
- Bi-endian support
- Runway system/memory bus, 125MHz, 64-bit, DDR (double data rate), about 2.0GB/s peak bandwidth
- Up to 440MHz frequency with 2.0V core voltage
- 21.3×22.0 mm2 die, 140,000,000 FETs, 0.25 micron, 5-layer metal CMOS packaged in a 544-pin LGA package