IBM POWER3 processors
Introduction: October 1998
The new 64-bit POWER3 processor, announced October 1998, unifies the POWER2 architecture (P2SC) with the PowerPC architecture, and was optimized for technical applications.
The SMP-capable POWER3 design allows for concurrent operation of fixed-point instructions, load/store instructions, branch instructions, and floating-point instructions. The POWER3 is capable of executing up to four floating-point operations per cycle (two multiply-add instructions). Integer performance has been significantly enhanced over the P2SC with the addition of dedicated integer and load/store execution units.
The chip features eight execution units fed by a 6.4 gigabyte-per-second memory subsystem. The core includes two high-bandwidth buses: a 128-bit 6XX architecture bus to main memory and 256-bit bus to the L2 cache that runs at processor speed. The POWER3 also has on-chip 64KB data cache and a 32KB instruction cache.
IBM's first 64-bit symmetric multiprocessor (SMP) workstation is the POWER3 based RS/6000 43P 7043-260 (200MHz).