Gecko's CPU Library

Hewlett Packard PA-8600 (Landshark) processors

Introduction: January 2000

The PA-8600 basically was just a PA-8500 with minor modifications to make it fit onto a new manufacturing process in order to achieve higher clock speeds. One of the only real changes applied to the original design was a quasi LRU replacement policy for the instruction cache. Moreover, the interface to the Runway bus apparently was slightly modified, and the order of the bus transaction reworked.

PA-8600 was used in A400-5X (rp2400), A500-5X (rp2450), B2000 (some), B2600, C3600, J5600, J6000, J7600, L1000-5X (rp5400), L2000-5X (rp5450), L1500-5X (rp5430), L3000-5X (rp5470), N4000-5X (rp7400), V2600, Superdome and Stratus Continuum 439, 449, 651-2, 652-2, 1251-2, 1252-2.

- PA-RISC version 2.0 64-bit
- Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
- 4-way superscalar
- Two address adders
- 160-entry fully-associative dual-ported TLB
- 32-entry BTAC (Branch Target Address Cache)
- 2048-entry BHT (Branch History Table)
- Dynamic and static branch prediction modes
- On-chip L1 caches 0.5MB I and 1MB D, each 4-way set associatve
- 32 or 64 Byte cache line size
- Supports up to 1 TB of physically addressable memory (40-bit physical addresses)
- 56-entry instruction queue/reorder buffer (IRB)
- MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g. MPEG decoding
- Quasi LRU replacement policy for the instruction cache
- Bi-endian support
- Runway system/memory bus, 125MHz, 64-bit, DDR (double data rate), about 2.0GB/s peak bandwidth
- Up to about 550MHz frequency with 2.0V core voltage
- 21.3×22.0 mm2 die, 140,000,000 FETs, 0.25 micron, 5-layer metal CMOS packaged in a 544-pin LGA package