Gecko's CPU Library

AMD Duron (Spitfire, Morgan, Appaloosa, Applebred) processors

Introduction: June 2000 (Spitfire), August 2001 (Morgan), August 2003 (Applebred)


The AMD Duron was an x86-compatible computer processor manufactured by AMD. It was released on June 19, 2000 as a low-cost alternative to AMD's own Athlon processor and the Pentium III and Celeron processor lines from rival Intel. The Duron was discontinued in 2004 and succeeded by the Sempron.

The Spitfire, Morgan, Appaloosa and Applebred cores

The Duron was pin-compatible with the Athlon and carried all of the computational resources from it, operating on the same motherboards in most cases. The original Duron was limited to operating on a 100MHz front-side bus speed (FSB 200), while the Athlon at the time could run on a bus clock of 133MHz (FSB 266). Later Durons supported a 133MHz bus (FSB 266) while Athlon XP ran at 166/200MHz FSB (FSB 333/400). The original Duron, using the "Spitfire" core, was manufactured in 2000 and 2001 at speeds ranging from 600 to 950MHz. It was based on the 180nm "Thunderbird" Athlon core. The second-generation Duron, the "Morgan" core, was sold in speed grades between 900 and 1300MHz, and was based on the 180 nm "Palomino" Athlon XP core. As a result, it featured a few important enhancements namely full Intel SSE support, enlarged TLBs, hardware data prefetch, and an integrated thermal diode. Like the "Palomino" core, "Morgan" was also expected to reduce the core heat dissipation, however in "Morgan"'s case this did not happen due to its increased core voltage. The final generation Duron was called "Applebred", sometimes called "Appalbred", and was based on the "Appaloosa" Duron along with the 130nm "Thoroughbred" Athlon XP. "Appaloosa" was never officially announced but it did see very limited circulation.

Duron's biggest difference from Athlon was its reduction in cache size to 64KB, in contrast to the 256KB or even 512KB of Athlon. This was a relatively tiny amount of L2 cache, even smaller than the 128KB L2 on Intel's Celeron. However, the K7-architecture enjoyed one of the largest L1 caches, at 128KB (split 64+64KB). And, with the arrival of the socketed Athlon/Duron chips, AMD switched to an exclusive cache design which did not mirror data between the L1 and L2 like the inclusive cache used on the Slot A K7, a critical feature in a low-cache situation. An exclusive design greatly favors L1 cache as the primary caching resource, while the slower L2 cache stores victim or copy-back cache blocks to be written back to main memory (LRU). The L2 cache essentially acts as an overflow from the L1 cache. Because of the lack of duplication between caches, Duron can be said to have 192KB cache onboard, whereas an inclusive chip such as Athlon Slot-A, with 512KB L2, would only have, in practice, 512KB total (640K-128K). Celeron was in the same boat with its inclusive cache for a total of 128KB (160K-32K).

Consequently, the post-Slot-A K7-architecture was less sensitive to L2 cache size. This reduced reliance upon L2 cache also allowed AMD to make their L2 cache higher latency and lower bandwidth without significant performance loss, which lessened processor complexity and allowed better manufacturing yields. AMD's Duron "Spitfire" CPU was only roughly 10% slower than its big brother, Athlon "Thunderbird".

Duron was often a favorite of computer builders looking for performance while on a tight budget. Perhaps most notably, in 2003 the "Applebred" Duron was available in 1.4GHz, 1.6GHz and 1.8GHz forms, all on a 133MHz (FSB 266) bus by default. Enthusiast groups discovered these Durons to be rebadged Thoroughbred A/B cores with cache disabled (and perhaps defective). With some research and testing it was found that "Applebred" could be turned into "Thoroughbred" Athlon XP, with full 256KB cache, at a very high success rate with "Thoroughbred B" cores. However, this was only possible for a period of approximately 4 weeks, as shortly after the Applebred was released AMD changed the chip configuration method to one that was not changeable.

Source: Wikipedia, the free encyclopedia.