Gecko's CPU Library

Hewlett Packard PA-8700 (Piranha) processors

Introduction: August 2001

The PA-8700 is basically an enhanced and revamped PA-8500 core with some slight modifications. As all PA-8x00 CPUs before, it logically still is very close to the original PA-8000 core from 1997. All subsequent new CPUs from HP were based on this design and added several features and some slight modifications to it while retaining the basic PA-RISC version 2.0 core. The PA-8700 enhanced the on-chip L1 caches and the TLB significantly while switching to a new CMOS-process helped boosting the clock-frequency. The chip was at its time one of the largest available commercial CPUs and one of the first to be manufactured in a SOI (Silicon On Insulator) process. The PA-8700 was manufactured by IBM, in contrast to the PA-8500 and PA-8600, which were fabbed by Intel, after HP gave up its processor fabs long time ago.

PA-8700 was used in A400-6X (rp2430), A500-6X, A500-7X (rp2470), C3650, C3700, C3750, J6700, L1500-6X, L1500-7X, L1500-8X (rp5430), L3000-6X, L3000-7X, L3000-8X (rp5470), N4000-6X, N4000-7X (rp7400), N4000-6X, N4000-7X, N4000-8X (rp7405, rp7410) and Superdome.

- PA-RISC version 2.0 64-bit
- Ten functional units: 2 integer ALUs, 2 shift/merge units, 2 complete load/store pipelines, 2 Floating Point multiply/accumulate units, 2 Floating Point divide/square root units
- 4-way superscalar
- Two address adders
- 240-entry fully-associative dual-ported TLB
- 32-entry BTAC (Branch Target Address Cache)
- 2048-entry BHT (Branch History Table)
- Dynamic and static branch prediction modes
- 0.75MB I and 1.5MB D on-chip L1 caches, each 4-way set associatve, implemented in independent 0.75MB banks
- 32 or 64 Byte cache line size
- Data cache prefetching
- Quasi LRU replacement policy for both the instruction and data cache
- Supports up to 16 TB of physically addressable memory (44-bit physical addresses)
- 56-entry instruction queue/reorder buffer (IRB)
- MAX-2 multimedia extensions (subword arithmetic) for multimedia applications, e.g. MPEG decoding
- Bi-endian support
- Support for hardware lock-stepping, i.e. operating multiple chips in parallel to detect faults
- Runway system/memory bus, 125MHz, 64-bit, DDR (double data rate), about 2.0GB/s peak bandwidth
- Up to 750MHz (875MHz on the PA-8700+) frequency with 1.5V core voltage
- 16.0×19.0 mm2 die, 186,000,000 FETs, 0.18 micron, 7-layer Silicon-on-Insulator CMOS packaged in a 544-pin LGA package