Gecko's CPU Library

AMD Athlon 64 (Clawhammer, Newcastle, Winchester, Venice, San Diego) processors

Introduction: September 2003 (Clawhammer), December 2003 (Newcastle), October 2004 (Winchester), April 2005 (Venice and San Diego)


The Athlon 64 was an eighth-generation, AMD64 architecture microprocessor produced by AMD, released on September 23, 2003. It was the third processor to bear the name Athlon, and the immediate successor to the Athlon XP. The second processor (after the Opteron) to implement AMD64 architecture and the first 64-bit processor targeted at the average consumer, it was AMD's primary consumer microprocessor, and competed primarily with Intel's Pentium 4, especially the "Prescott" and "Cedar Mill" core revisions. It was AMD's first K8, eighth-generation processor core for desktop and mobile computers. Despite being natively 64-bit, the AMD64 architecture was backward-compatible with 32-bit x86 instructions. Athlon 64s had been produced for Socket 754, Socket 939, Socket 940, and Socket AM2.

The Clawhammer, Newcastle, Winchester, Venice and San Diego cores

The Athlon 64 was originally codenamed Clawhammer by AMD, and was referred to as such internally and in press releases. The first Athlon 64 FX was based on the first Opteron core, SledgeHammer. Both cores, produced on a 130 nanometer process, were first introduced on September 23, 2003. The models first available were the FX-51, fitting Socket 940, and the 3200+, fitting Socket 754. Like the Opteron, on which it was based, the Athlon FX-51 required buffered RAM, increasing the final cost of an upgrade. The week of the Athlon 64's launch, Intel released the Pentium 4 Extreme Edition, a CPU designed to compete with the Athlon 64 FX. The Extreme Edition was widely considered a marketing ploy to draw publicity away from AMD, and was quickly nicknamed among some circles the "Emergency Edition". Despite a very strong demand for the chip, AMD was plagued by early manufacturing difficulties that made it difficult to deliver Athlon 64s in quantity. In the early months of the Athlon 64 lifespan, AMD could only produce one hundred thousand chips per month. However, it was very competitive in terms of performance to the Pentium 4, with magazine PC World calling it the "fastest yet". "Newcastle" was released soon after Clawhammer, with half the Level 2 cache.

On June 1, 2004, AMD released new versions of both the Clawhammer and Newcastle core revisions for the newly-introduced Socket 939, an altered Socket 940 without the need for buffered memory. Socket 939 offered two main improvements over Socket 754: the memory controller was altered with dual-channel architecture, doubling peak memory bandwidth, and the HyperTransport bus was increased in speed from 800MHz to 1000MHz. Socket 939 also was introduced in the FX series in the form of the FX-55. At the same time, AMD also began to ship the "Winchester" core, based on a 90 nanometer process.

Core revisions "Venice" and "San Diego" succeeded all previous revisions on April 15, 2005. Venice, the lower-end part, was produced for both Sockets 754 and 939, and included 512KB of L2 cache. San Diego, the higher-end chip, was produced only for Socket 939 and doubled Venice's L2 cache to 1MB. Both were produced on the 90 nm fabrication process. Both also included support for the SSE3 instruction set, a new feature that had been included in the rival Pentium 4 since the release of the Prescott core in February 2004. In addition, AMD overhauled the memory controller for this revision, resulting in performance improvements as well as support for newer DDR RAM.

The memory controller used in all DDR2 SDRAM capable processors (Socket AM2), has extended column address range of 11 columns instead of conventional 10 columns, and the support of 16KB page size, with at most 2048 individual entries supported. An OCZ unbuffered DDR2 kit, optimized for 64-bit operating systems, was released to exploit the functionality provided by the memory controller in socket AM2 processors, allowing the memory controller to stay longer on the same page, thus benefitting graphics intensive applications.

Common among the Athlon 64 line are a variety of instruction sets including MMX, 3DNow!, SSE, SSE2, and SSE3. All Athlon 64s also support the NX bit, a security feature named "Enhanced Virus Protection" by AMD. And as implementations of the AMD64 architecture, all Athlon 64 variants are able to run 16 bit, 32 bit x86, and AMD64 code, through two different modes the processor can run in: "Legacy mode" and "Long mode". Legacy mode runs 16-bit and 32-bit programs natively, and Long mode runs 64-bit programs natively, but also allows for 32-bit programs running inside a 64-bit operating system. All Athlon 64 processors feature 128KB of level 1 cache, and at least 512KB of level 2 cache.

The Athlon 64 features an on-die memory controller, a feature not previously seen on x86 CPUs. Not only does this mean the controller runs at the same clock rate as the CPU itself, it also means the electrical signals have a shorter physical distance to travel compared to the old northbridge interfaces. The result is a significant reduction in latency (response time) for access requests to main memory. The lower latency is often cited as one of the advantages of the Athlon 64's architecture over those of its competitors.

Translation Lookaside Buffers (TLBs) have also been enlarged (40 4KB/2MB/4MB entries in L1 cache, 512 4KB entries), with reduced latencies and improved branch prediction, with four times the number of bimodal counters in the global history counter. This and other architectural enhancements, especially as regards SSE implementation, improve instruction per cycle (IPC) performance over the previous Athlon XP generation. To make this easier for consumers to understand, AMD has chosen to market the Athlon 64 using a PR (Performance Rating) system, where the numbers roughly map to Pentium 4 performance equivalents, rather than actual clock speed.

Athlon 64 also features CPU speed throttling technology branded Cool'n'Quiet, a feature similar to Intel's SpeedStep that can throttle the processor's clock speed back to facilitate lower power consumption and heat production. When the user is running undemanding applications and the load on the processor is light, the processor's clock speed and voltage are reduced. This in turn reduces its peak power consumption (max TDP set at 89W by AMD) to as low as 32W (stepping C0, clock speed reduced to 800MHz) or 22W (stepping CG, clock speed reduced to 1GHz). The Athlon 64 also has an Integrated Heat Spreader (IHS) which prevents the CPU core from accidentally being damaged when mounting and unmounting cooling solutions. With prior AMD CPUs a CPU shim could be used by people worried about damaging the core.

The Athlon 64 CPUs have been produced with 130 nm and 90 nm SOI process technologies. All of the latest chips (Winchester, Venice and San Diego models) are on 90 nm. The Venice and San Diego models also incorporate dual stress liner technology (an amalgam of strained silicon and squeezed silicon, the latter of which is not actually a technology) co-developed with IBM.

To summarize, the Athlon 64 architecture features two buses from the CPU. One is the HT bus to the northbridge connecting the CPU to the chipset and device attachment bus (PCIe, AGP, PCI) and the other is the memory bus which connects the on-board memory controller to the bank of either DDR or DDR2 DRAM.

Source: Wikipedia, the free encyclopedia.