Gecko's CPU Library

Hewlett Packard PA-8800 (Mako) processors

Introduction: 2004

The PA-8800 integrates two PA-8700 cores onto a single die, adds a very large off-die L2 cache (though with a very significant bandwidth) onto the CPU module, enhances the clock frequency a bit further and uses the Itanium2 McKinley processor/system bus. Mako was supposed to breathe fresh life in the PA-RISC line, though it had strong internal competition from the Itanium line (based on much HP development; with Intel) and as such was not marketed much. Most systems which could handle a PA-8800 use the HP zx1 chipset and could be hardware-upgraded to use Itanium 2/IA64 processors.

PA-8800 was used in C8000, L1500-9X (rp5430), L2000-9X (rp5450), N4000-9X (rp7405, rp7410), rp3410, rp3440, rp4410, rp4440, rp7420, rp8400, rp8410, rp8420 and Superdome.

- PA-RISC version 2.0 64-bit
- Twenty functional units: four integer ALUs, four shift/merge units, four complete load/store pipelines, four Floating Point multiply/accumulate units, four Floating Point divide/square root units
- 4-way superscalar
- Two address adders
- 240-entry fully-associative dual-ported TLB per core
- 32-entry BTAC (Branch Target Address Cache) per core
- 2048-entry BHT (Branch History Table) per core
- Dynamic and static branch prediction modes
- 0.75MB I and 0.75MB D on-chip L1 caches per core
- No data passing between the cores’ L1 caches
- 32MB off-chip L2 cache, four-way associative, physically indexed and tagged
- L2 cache is shared between both CPU cores
- L2 cache controller is on-die
- L2 implemented in DDR-ESRAM, four 8MB chips, 300MHz clock, each 2.7GB/s bandwidth
- Total >10GB/s L2 cache bandwidth
- 1MB SRAM tags for L2 cache
- ECC for L2 data and tags
- Itanium 2 McKinley processor bus, 200MHz clock (double-pumped), 128-bit datapath, 6.4GB/s bandwidth, data ECC-protected, signals parity
- Up to 1GHz frequency with 1.5V core voltage
- 23.6×15.5 mm2 die, 300,000,000 FETs, 0.13 micron, 8-layer Silicon-on-Insulator CMOS (fabbed by IBM)