Gecko's CPU Library

VIA C7 (Esther) processors

Introduction: May 2005


The VIA C7 was an x86 central processing unit designed by Centaur Technology and sold by VIA Technologies. It delivered a number of improvements to the older VIA C3 cores but was nearly identical to the latest VIA C3 Nehemiah core. The C7 was officially launched in May 2005, although according to market reports, full volume production was not in place at that date. In May 2006 Intel's cross-licensing agreement with VIA expired and was not renewed, which was the reason for the forced termination of C3 shipments on March 31, 2006, as VIA lost rights to the socket 370. The C7 appeared still to be found in the marketplace, for example, on the bargain-priced Everex TC2502, sold by Wal-Mart with a Linux distribution preinstalled.

The C7 was sold in three main versions:
- C7: for desktops/laptops (1.5-2.0GHz) in FCPGA Pentium M package, 400/533/800MHz FSB
- C7-M: for mobiles/embedded (1.5-2.0GHz) in 21 mm x 21 mm NanoBGA2, 400/800MHz FSB
- C7-M Ultra Low Voltage: for mobiles/embedded (1.0-1.6GHz) in 21 mm x 21 mm NanoBGA2, 400/800MHz FSB
- C7-D: similar to original C7, but RoHS-compliant and marketed as "carbon-free processor". Some variants did not support PowerSaver.

The Esther core

The Esther (C5J) was the next evolution step of the Nehemiah+ (C5P) core of the VIA C3 line-up, including a migration to a 90 nm silicon on insulator (SOI) manufacturing process developed by IBM Microelectronics. The processors were produced in IBM's fab in East Fishkill, New York. The chip was designed by Centaur Technology in Austin, Texas, by a permanent staff of 85 engineers.

New Features of this core included:
- Average power consumption of less than 1 watt
- 2GHz operation and a TDP of 20 watts
- Level 2 cache increased from 64KB to 128KB, with associativity increased from 16-way set associative in C3 to 32-way set associative in C7
- VIA had stated the C7 bus was physically based upon the Pentium M 479-pin packaging, but used the proprietary VIA V4 bus for electrical signalling, instead of Intel’s AGTL+ Quad Pumped Bus, avoiding legal infringement
- "Twin Turbo" technology, which consisted of dual PLLs, one set at a high clock speed, and the other set at a lower speed. This allowed the processor's clock frequency to be adjusted in a single processor cycle, much faster than the comparable Intel SpeedStep technology, providing enhanced power savings.
- Support for SSE2 and SSE3 extended instructions
- NX bit in PAE mode that prevented buffer overflow software bugs from being exploitable by viruses or attackers
- Hardware support for SHA-1 and SHA-256 hashing
- Hardware based "Montgomery Multiplier" supporting key sizes up to 32KB for public key cryptography

Source: Wikipedia, the free encyclopedia.