Gecko's CPU Library

POWER architecture

Introduction: 1990

POWER architecture began its life at IBM in the late 1980s when they wanted a high performance RISC architecture for their mid range workstations and servers. The result was the POWER architecture with its first implementation in 1990 in the RISC System/6000, later RS/6000, computers. This was the 11-chips RIOS processor, later called POWER1. The RISC Single Chip (RSC) processor was developed from RIOS.

POWER is a backronym for Performance Optimization With Enhanced RISC.

The instruction set architecture is divided into several categories and every component is defined as a part of a category. And each category resides within a certain Book. Processors implement a set of these categories. Different classes of processors are required to implement certain categories, for example a server class processor use categories Server, Base, Floating Point, 64-bit, etc. All processors implement the Base category.

It is a RISC load/store architecture. It has multiple set of registers:
- 32 32-bit or 64-bit General Purpose Registers (GPRs) for integer operations
- 32 64-bit Floating Point Registers (FPRs) for floating point operations
- 32 128-bit vector registers for vector operations
- 8 4-bit Condition Register fields (CRs) for comparison and flow control
- Special registers: Counter Register (CTR), Link Register (LR), Time Base (TBU, TBL), Alternate Time Base (ATBU, ATBL), Accumulator (ACC), status registers (XER, FPSCR, VSCR, SPEFSCR)

Instructions have a 4-byte (32-bit) uniform length with the exception of the VLE (Variable-Length Encoding) subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precision IEEE-754 compliant floating point operations are supported with additional multiply add instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction.

Support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. Support for both big and little-endian addressing with separate categories for moded and per-page endianess. Support for both 32-bit and 64-bit addressing. Different modes of operation: User, supervisor and hypervisor.

- Base: Most of Book I and Book II
- Server: Book III-S
- Embedded: Book III-E
- Misc: Floating Point, Vector, Signal Processing, Cache Locking, Decimal Floating-point, etc.

- Book I: User Instruction Set Architecture covers the base instruction set available to the application programmer. Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. It includes chapters regarding auxiliary processing units like DSPs and the AltiVec extension.
- Book II: Virtual Environment Architecture defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering.
- Book III: Operating Environment Architecture includes exceptions, interrupts, memory management, debug facilities and special control functions. It's divided into two parts. Book III-S defines the supervisor instructions used for general purpose/server implementations. It's mainly the contents of the Book III of the former PowerPC ISA. Book III-E Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E.
- Book VLE: Variable Length Encoded Instruction Architecture defines alternative instructions and definitions from Book I-III, intended for higher instruction density and very low end applications. They use 16-bit instructions and big endian byte ordering.

Source: Wikipedia, the free encyclopedia.